The present application relates to semiconductor device fabrication, and more particularly, to the fabrication of III-V compound semiconductor fin field effect transistors (FinFETs) with improved fin height control.
III-V compound semiconductors are promising channel materials for n-channel transistors in complementary metal-oxide semiconductor (CMOS) circuits due to their high electron mobility as compared to current silicon-based channel. Aspect ratio trapping (ART) has been explored as a viable approach to grow high quality III-V compound semiconductor fins in trenches by trapping defects at lower trench portions. Typically a III-V compound semiconductor fin (e.g., InGaAs) grown by ART requires first growing an insulating or semi-insulating III-V compound material fin (e.g., InP) and then recessing the insulating or semi-insulating III-V compound material fin followed by III-V compound semiconductor fin growth.
However, because the etch rate across the wafer is typically not uniform, the non-uniform etch rate causes height variations in the recessed insulating or semi-insulating III-V compound material fin, which, in turn, can lead to significant height variations in the III-V compound semiconductor fins subsequently formed thereon. The non-uniform channel fin heights can result in significant variations in device performance. Therefore, methods that allow better control of fin heights in forming III-V compound semiconductor fins by ART remain needed.